1. Technical Field of the Invention
This invention relates to the construction of an isolation trench or slot in an integrated circuit structure. More particularly, this invention relates to an improved method for planarizing an isolation slot to eliminate the deleterious effects of microcracks, discontinuities, or voids occurring in the material used to fill the isolation slot for planarization.
2. Description of the Prior Art
Isolation slots or trenches are utilized in integrated circuit structures to provide a barrier in the silicon substrate between adjacent active devices. Such an isolation technique is described in Bondur et al U.S. Pat. No. 4,104,086. After initial formation of the slot, the walls are oxidized to form a silicon dioxide dielectric which provides the desired electrical isolation between adjacent active devices in the silicon substrate.
To prevent or inhibit formation of a step in overlying layers, it is desirable to completely fill the slot. This could be done by growing sufficient oxide within the slot. However, since silicon oxide occupies a larger volume than the silicon from which it is grown, attempts to completely fill the slot with oxide can result in the formation of stresses which may ultimately damage the structure. Alternatively, growing sufficient oxide to fill the slot can result in the creation of voids due to the tendency of the oxide to neck in at the top of the slot depending upon the slot dimensions. Subsequent etch back of the oxide then can result in opening of the void which can have undesirable consequences. Therefore, the remainder of the slot is preferably filled with polysilicon to permit subsequent planarization.
However, even the use of polysilicon is not without difficulties. The polysilicon deposited in the slot over the isolation oxide may also tend to neck in at the top of the slot thereby creating an unfilled volume or void below. Even when a void is not created, a microcrack, or discontinuity may be created where the deposited polysilicon on the sidewalls of the slot finally touch when the width of the slot is less than one-half of the depth. Since it is usually desirable to provide a slot having a minimum width from a space standpoint, this condition frequently occurs. Subsequent oxidation of the structure for planarization or isolation purposes, e.g., in multilayer structures, can result in stress formation if the oxidizing conditions penetrate the void, discontinuity, or crack in the polysilicon.
The use of multistep techniques to alleviate the effects of voids in materials used for planarization is known. Thomas et al U.S. Pat. No. 4,481,070, assigned to the assignee of this invention, describes and claims such a technique for mitigating the effects of such voids formed in silicon dioxide between closely spaced together metal lines when growing silicon dioxide to planarize an integrated circuit structure.
However, when an oxidizable material is used for planarization purposes, the amount removed by etching during planarization must be further interrelated to the penetration of subsequently grown oxide therein. This is because the growth of an oxide on or in the surface of an oxidizable material consumes a portion of the oxidizable material and thus effectively penetrates below the former surface of the oxidizable material. For example, the oxidation of polysilicon results in the growth of polysilicon dioxide having a thickness which extends about 55% above the preexisting surface of the polysilicon and about 45% below the surface. Any attempts to provide multistep polysilicon deposition for planarization must take this oxide penetration into account to be effective.